Name Strings

SPV_ALTERA_fpga_invocation_pipelining_attributes

Contact

To report problems with this extension, please open a new issue at:

https://github.com/KhronosGroup/SPIRV-Registry

Contributors

  • Jessica Davies, Intel

  • Joe Garvey, Intel

  • Mike Kinsner, Intel

Notice

Copyright (c) 2021 Intel Corporation. All rights reserved.

Status

Final draft

Version

Last Modified Date

2021-05-21

Revision

1

Dependencies

This extension is written against the SPIR-V Specification, Version 1.5 Revision 3.

This extension requires SPIR-V 1.0.

Overview

Some FPGA devices and toolchains can support customizable levels or implementation of pipeline parallelism when mapping a SPIR-V module to hardware. Through pipeline parallelism, multiple invocations of a kernel or function can execute concurrently.

This extension adds decorations to request that a kernel or function support invocations at a specified initiation interval, that multiple invocations are forbidden from executing concurrently, or that the kernel or function is limited to a maximum number of concurrent invocations.

Extension Name

To use this extension within a SPIR-V module, the following OpExtension must be present in the module:

OpExtension "SPV_ALTERA_fpga_invocation_pipelining_attributes"

New capabilities

This extension introduces a new capability:

FPGAInvocationPipeliningAttributesALTERA

New Decorations

This extension adds the following decorations under the FPGAInvocationPipeliningAttributesALTERA capability:

InitiationIntervalALTERA
MaxConcurrencyALTERA
PipelineEnableALTERA

Token Number Assignments

FPGAInvocationPipeliningAttributesALTERA

5916

InitiationIntervalALTERA

5917

MaxConcurrencyALTERA

5918

PipelineEnableALTERA

5919

Modifications to the SPIR-V Specification, Version 1.5

Decoration

Modify Section 3.20, Decoration, adding these rows to the Decoration table:

Decoration Extra Operands Enabling Capabilities

5917

InitiationIntervalALTERA
Only valid on OpFunction. Strong request, to the extent possible, for this function to support an initiation interval of Cycles clock cycles. Cycles is a 32-bit unsigned integer type scalar. The value of Cycles must be non-zero.

Literal
Cycles

FPGAInvocationPipeliningAttributesALTERA

5918

MaxConcurrencyALTERA
Only valid on OpFunction. Strong request, to the extent possible, to allow no more than a fixed number Invocations of invocations to execute the function concurrently. Invocations is a 32-bit unsigned integer type scalar. If Invocations is equal to zero, it indicates no limit on the number of concurrent invocations.

Literal
Invocations

FPGAInvocationPipeliningAttributesALTERA

5919

PipelineEnableALTERA
Only valid on OpFunction. Strong request, to the extent possible, to either support pipelining or to not pipeline invocations of this function. Enable is a 32-bit unsigned integer type scalar. If Enable is equal to 0, it indicates a request not to pipeline, while a non-zero value indicates a request to pipeline.

Literal
Enable

FPGAInvocationPipeliningAttributesALTERA

Capability

Modify Section 3.31, Capability, adding a row to the Capability table:

Capability Implicitly Declares

5916

FPGAInvocationPipeliningAttributesALTERA

Kernel

Validation Rules

None.

Issues

None.

Revision History

Rev Date Author Changes

1

2021-05-21

Jessica Davies

Initial public release