Name Strings
SPV_AMDX_shader_enqueue
Contact
See Issues list in the Khronos SPIRV-Headers repository: https://github.com/KhronosGroup/SPIRV-Headers
Provisional
This extension is provisional and should: not be used in production applications. The functionality may change in ways that break backwards compatibility between revisions, and before final release.
Contributors
-
Tobias Hector, AMD
-
Matthäus Chajdas, AMD
-
Nicolai Hähnle, AMD
-
Junda Liu, AMD
-
Maciej Jesionowski, AMD
-
Daniel Brown, AMD
-
Stuart Smith, AMD
Notice
Copyright (c) 2024 The Khronos Group Inc. Copyright terms at http://www.khronos.org/registry/speccopyright.html
Status
Provisional.
Version
Last Modified Date |
2024-07-26 |
Revision |
2 |
Dependencies
This extension is written against the Unified SPIR-V Specification, Version 1.6, Revision 1.
This extension requires SPIR-V 1.4.
Overview
This extension adds the ability for developers to enqueue compute and mesh shader workgroups from compute shaders.
Extension Name
To use this extension within a SPIR-V module, the following OpExtension must be present in the module:
OpExtension "SPV_AMDX_shader_enqueue"
Capabilities
Modify Section 3.31, "Capability", adding this row to the table:
Capability | Enabling Capabilities | |
---|---|---|
5067 |
ShaderEnqueueAMDX |
Shader |
Storage Class
Modify Section 3.7, "Storage Class", adding this row to the table:
Storage Class | Enabling Capabilities | |
---|---|---|
5068 |
NodePayloadAMDX |
ShaderEnqueueAMDX |
Execution Modes
Modify Section 3.6, "Execution Mode", adding the following rows to the table:
Execution Mode | Extra Operands | Enabling Capabilities | |||
---|---|---|---|---|---|
5069 |
CoalescingAMDX |
ShaderEnqueueAMDX |
|||
5071 |
MaxNodeRecursionAMDX |
<id> |
ShaderEnqueueAMDX |
||
5070 |
IsApiEntryAMDX |
<id> |
ShaderEnqueueAMDX |
||
5072 |
StaticNumWorkgroupsAMDX |
<id> |
<id> |
<id> |
ShaderEnqueueAMDX |
5077 |
MaxNumWorkgroupsAMDX |
<id> |
<id> |
<id> |
ShaderEnqueueAMDX |
5073 |
ShaderIndexAMDX |
<id> |
ShaderEnqueueAMDX |
||
5102 |
SharesInputWithAMDX |
<id> |
<id> |
ShaderEnqueueAMDX |
Decorations
Modify Section 3.20, "Decoration", adding the following row to the table:
Decoration | Extra Operands | Enabling Capabilities | |
---|---|---|---|
5020 |
NodeMaxPayloadsAMDX |
<id> |
ShaderEnqueueAMDX |
5019 |
NodeSharesPayloadLimitsWithAMDX |
<id> |
ShaderEnqueueAMDX |
5091 |
PayloadNodeNameAMDX |
<id> |
ShaderEnqueueAMDX |
5098 |
PayloadNodeBaseIndexAMDX |
<id> |
ShaderEnqueueAMDX |
5099 |
PayloadNodeSparseArrayAMDX |
ShaderEnqueueAMDX |
|
5100 |
PayloadNodeArraySizeAMDX |
<id> |
ShaderEnqueueAMDX |
5078 |
TrackFinishWritingAMDX |
ShaderEnqueueAMDX |
|
5105 |
PayloadDispatchIndirectAMDX Must decorate a structure member with a type of OpTypeInt or OpTypeVector with two or three components. The integer type or the type of the vector component must be an OpTypeInt with up to 32-bit Width and 0 Signedness. If a single integer is used, the Y and Z dispatch indirect arguments are assumed to be 1. If a vector of two components is used, the Z dispatch indirect argument is assumed to be 1. |
ShaderEnqueueAMDX |
Builtins
Modify Section 3.21, "BuiltIn", adding the following row to the table:
BuiltIn | Enabling Capabilities | |
---|---|---|
5021 |
RemainingRecursionLevelsAMDX |
ShaderEnqueueAMDX |
5073 |
ShaderIndexAMDX |
ShaderEnqueueAMDX |
Instructions
Add the following new instructions:
OpTypeNodePayloadArrayAMDX |
Capability: |
||
3 |
5076 |
Result <id> |
<id> |
OpNodePayloadArrayLengthAMDX |
Capability: |
|||
4 |
5090 |
<id> |
Result <id> |
<id> |
Validation Rules
In section 2.16, Validation Rules for Shader Capabilities, Add NodePayloadAMDX to the list of storage classes where composite variables must be explicitly laid out.
Issues
-
None
Revision History
Rev | Date | Author | Changes |
---|---|---|---|
1 |
2023-07-22 |
Tobias Hector |
Initial revision. |
2 |
2024-07-26 |
Tobias Hector |
Update to better match HLSL |