Name Strings

SPV_INTEL_cache_controls

Contact

To report problems with this extension, please open a new issue at:

https://github.com/KhronosGroup/SPIRV-Registry

Contributors

  • Andrzej Ratajewski, Intel

  • Ben Ashbaugh, Intel

  • Dmitry Sidorov, Intel

  • Gregory Lueck, Intel

  • Victor Mustya, Intel

Notice

Copyright (c) 2023 Intel Corporation. All rights reserved.

Status

Complete.

Version

Last Modified Date

2023-08-28

Revision

1

Dependencies

This extension is written against the SPIR-V Specification, Version 1.6, Revision 2.

This extension requires SPIR-V 1.0

Overview

This extension allows cache control information to be applied to memory access instructions.

The cache controls are a strong request that the SPIR-V consumer should use a memory operation with the indicated cache controls. However, the SPIR-V consumer may choose a different cache control if the requested one is unsupported or for any other reason. The cache controls may affect the performance of a program, but (with very few exceptions) must not affect the functional correctness.

Extension Name

To use this extension within a SPIR-V module, the appropriate OpExtension must be present in the module:

OpExtension "SPV_INTEL_cache_controls"

New Capabilities

This extension introduces new capabilities:

CacheControlsINTEL

New Decorations

CacheControlLoadINTEL
CacheControlStoreINTEL

Token Number Assignments

CacheControlsINTEL

6441

CacheControlLoadINTEL

6442

CacheControlStoreINTEL

6443

Modifications to the SPIR-V Specification, Version 1.6, Revision 2

Validation Rules

Modify Section 2.16.1, Universal Validation Rules, adding the following statements.

  • Decoration rules

    • A CacheControlLoadINTEL Decoration must be applied only as follows:

      • Only OpTypePointer values can be decorated.

      • Pointer types of the decorated instructions must have Function, UniformConstant, CrossWorkgroup or Generic storage class.

      • It’s allowed to apply CacheControlLoadINTEL multiple times to the same Pointer.

      • Two CacheControlLoadINTEL decorations decorating the same Pointer must have different Cache Level values.

    • A CacheControlStoreINTEL Decoration must be applied only as follows:

      • Only OpTypePointer values can be decorated.

      • Pointer types of the decorated instructions must have Function, CrossWorkgroup or Generic storage class.

      • It’s allowed to apply CacheControlStoreINTEL multiple times to the same Pointer.

      • Two CacheControlStoreINTEL decorations decorating the same Pointer must have different Cache Level values.

Modify Section 3, Binary form, add new sub-sections after 3.18 Access Qualifier.

3.XX Load Cache Controls

Cache Control Enabling Capabilities Description

0

UncachedINTEL

CacheControlsINTEL

Hint that the load operation should not cache its data in the given cache level.

1

CachedINTEL

CacheControlsINTEL

Hint that the load operation should cache its data in the given cache level.

2

StreamingINTEL

CacheControlsINTEL

Hint that the load operation should cache its data in the specified cache level, using evict-first policy to minimize cache pollution caused by temporary streaming data that may only be accessed once or twice.

3

InvalidateAfterReadINTEL

CacheControlsINTEL

By using this control the SPIR-V generator is asserting that the cache line containing the data will not be read again until it’s overwritten, therefore the load operation can invalidate the cache line and discard "dirty" data. If the assertion is violated (the cache line is read again) then behavior is undefined.

4

ConstCachedINTEL

CacheControlsINTEL

By using this control the SPIR-V generator is asserting that the cache line containing the data will not be written until all invocations of the shader or kernel execution are finished. If the assertion is violated (the cache line is written), the behavior is undefined.

3.XX Store Cache Controls

Cache Control Enabling Capabilities Description

0

UncachedINTEL

CacheControlsINTEL

Hint that the store or atomic operation should not cache its data in the given cache level.

1

WriteThroughINTEL

CacheControlsINTEL

Hint that the store or atomic operation should immediately write data to the subsequent furthest cache, marking the cache line in the current cache as "not dirty".

2

WriteBackINTEL

CacheControlsINTEL

Hint that the store or atomic operation should write data into the given cache level and mark the cache line as "dirty". Upon eviction, "dirty" data will be written into the furthest subsequent cache.

3

StreamingINTEL

CacheControlsINTEL

Same as WriteThroughINTEL, but use evict-first policy to limit cache pollution by streaming output data.

Decorations

Modify Section 3.20, Decoration, adding rows to the Decoration table:

Decoration Extra Operands Enabling Capabilities

6442

CacheControlLoadINTEL
Apply the cache controls to a Pointer. The pointer must point to the Function, UniformConstant, CrossWorkgroup or Generic Storage Class.

If a memory-reading instruction uses the decorated pointer value as its input parameter, the decoration is a hint that the load operation should be performed with the specified cache semantics.

Cache Level is an unsigned 32-bit integer telling the cache level to which the control applies. The value 0 indicates the cache level closest to the processing unit, the value 1 indicates the next furthest cache level, etc. If some cache level does not exist, the decoration is ignored.

If the exact Load Cache Control value is unsupported, the consumer may apply implementation-specific closest match, but only if it does not change the observable effect of the requested Load Cache Control.

Literal
Cache Level

Load_Cache_Control
Cache Control

CacheControlsINTEL

6443

CacheControlStoreINTEL
Apply the cache controls to a Pointer. The pointer must point to the Function, CrossWorkgroup or Generic Storage Class.

If a memory-writing or atomic instruction uses the decorated pointer value as its input parameter, the decoration is a hint that the store operation should be performed with the specified cache semantics.

Cache Level is an unsigned 32-bit integer telling the cache level to which the control applies. The value 0 indicates the cache level closest to the processing unit, the value 1 indicates the next furthest cache level, etc. If some cache level does not exist, the decoration is ignored.

If the exact Store Cache Control value is unsupported, the consumer may apply implementation-specific closest match, but only if it does not change the observable effect of the requested Store Cache Control.

Literal
Cache Level

Store_Cache_Control
Cache Control

CacheControlsINTEL

Capabilities

Modify Section 3.31, Capability, adding rows to the Capability table:

Capability Implicitly Declares

6441

CacheControlsINTEL

Issues

  1. How the consumer should work with shareable data with cached controls, if some cache level is non-coherent?
    RESOLVED: The cache controls defined as "hints" cannot break memory model. The consumer must insert extra flush or invalidate operations to maintain the memory model in case of non-coherent caches. The cache controls defined as "assertions" may break memory model, so users should take care on undefined behavior cases.

  2. How to mark an operation "uncached" on all the available cache levels?
    RESOLVED: Use Nontemporal Memory Operand defined in core SPIR-V spec instead of this extension.

Revision History

Rev Date Author Changes

1

2023-08-28

Victor Mustya

Initial public revision