Name Strings

SPV_INTEL_fpga_buffer_location

Contact

To report problems with this extension, please open a new issue at:

https://github.com/KhronosGroup/SPIRV-Headers

Contributors

  • Joe Garvey, Intel

  • Daniel Zhang, Intel

Notice

Copyright (c) 2023 Intel Corporation. All rights reserved.

Status

Final Draft

Version

Last Modified Date

2023-02-01

Revision

1

Dependencies

This extension is written against the SPIR-V Specification, Version 1.6 Revision 2.

This extension requires SPIR-V 1.0.

Overview

This extension adds a pointer decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer.

Extension Name

To use this extension within a SPIR-V module, the following OpExtension must be present in the module:

OpExtension "SPV_INTEL_fpga_buffer_location"

New Capabilities

This extension introduces a new capability:

FPGABufferLocationINTEL

Token Number Assignments

FPGABufferLocationINTEL

5920

BufferLocationINTEL

5921

Modifications to the SPIR-V Specification, Version 1.6

Decoration

Modify Section 3.20, Decoration, adding these rows to the Decoration table:

Decoration Extra Operands Enabling Capabilities

5921

BufferLocationINTEL
Apply only to a pointer. Indicates that the pointer must only point into the physical memory identified by the subsequent literal number operand. The exact semantics of the literal number are implementation defined.

Literal
Buffer Location ID

FPGABufferLocationINTEL

Capability

Modify Section 3.31, Capability, adding a row to the Capability table:

Capability Implicitly Declares

5920

FPGABufferLocationINTEL

Validation Rules

None.

Issues

None.

Revision History

Rev Date Author Changes

1

2023-02-01

Joe Garvey

Initial public release