SPV_INTEL_fpga_latency

Name Strings

SPV_INTEL_fpga_latency_control

Contact

To report problems with this extension, please open a new issue at:

https://github.com/KhronosGroup/SPIRV-Registry

Contributors

Shuo Niu, Intel

Notice

Status

Final Draft

Version

Last Modified Date

2022-11-28

Revision

Dependencies

This extension is written against the SPIR-V Specification, Version 1.6 Revision 2.

This extension requires SPIR-V 1.0.

This extension specifies interaction with the SPV_INTEL_blocking_pipes extension.

Overview

This extension adds two decorations to represent latency controls on the pointer accessed by load, store, pipe read and pipe write instructions.

The behavior is implementation-defined if the combination of constraints specified by the decorations cannot be satisfied. For example, if one constraint specifies instruction A should be scheduled after instruction B, while another constraint specifies instruction B should be scheduled after instruction A then that set of constraints is unsatisfiable.

Extension Name

To use this extension within a SPIR-V module, the following OpExtension must be present in the module:

OpExtension "SPV_INTEL_fpga_latency_control"

New Capabilities

This extension introduces a new capability:

FPGALatencyControlINTEL

New Decorations

Decorations added under the FPGALatencyControlINTEL capability:

LatencyControlLabelINTEL
LatencyControlConstraintINTEL

Token Number Assignments

FPGALatencyControlINTEL

6171

LatencyControlLabelINTEL

6172

LatencyControlConstraintINTEL

6173

Modifications to the SPIR-V Specification, Version 1.6

Decoration

Modify Section 3.20, Decoration, adding these rows to the Decoration table:

Decoration	Extra Operands	Enabling Capabilities
6172	LatencyControlLabelINTEL Apply to an object of type OpTypePointer or OpTypePipe. If that object is used as the pointer operand by an OpLoad or OpStore instruction (for OpTypePointer) or the pipe operand by an OpReadPipe, OpWritePipe, OpReadPipeBlockingINTEL, or OpWritePipeBlockingINTEL instruction (for OpTypePipe) then this decoration conveys latency control information about that instruction. Any such instructions will be referred to as the "labeled instructions" corresponding to the decoration. Latency Label is a 32-bit signed integer type scalar that labels the labeled instruction so that it may be referred to in LatencyControlConstraintINTEL decorations.	Literal Number Latency Label	FPGALatencyControlINTEL
6173	LatencyControlConstraintINTEL Apply to an object of type OpTypePointer or OpTypePipe. If that object is used as the pointer operand by an OpLoad or OpStore instruction (for OpTypePointer) or the pipe operand by an OpReadPipe, OpWritePipe, OpReadPipeBlockingINTEL, or OpWritePipeBlockingINTEL instruction (for OpTypePipe) then this decoration conveys latency control information about that instruction. Any such instructions will be referred to as the "constrained instructions" corresponding to the decoration. Relative To, Control Type, and Relative Cycle constrain the cycle on which the constrained instruction can be scheduled. Relative To is a 32-bit signed integer type scalar that identifies the labeled instruction relative to which the constrained instruction associated with this decoration is being constrained. It corresponds to the Latency Label operand of a LatencyControlLabelINTEL decoration. Relative Cycle is a 32-bit signed integer type scalar whose meaning depends on Control Type. Control Type is a 32-bit signed integer type scalar that represents the type of the constraint. If Control Type is equal to 1, it indicates that the latency between the labeled instruction and the constrained instruction should be exactly Relative Cycle cycles. If Control Type is equal to 2, it indicates that the latency between the labeled instruction and the constrained instruction should be at most Relative Cycle cycles. If Control Type is equal to 3, it indicates that the latency between the labeled instruction and the constrained instruction should be at least Relative Cycle cycles.	Literal Number Relative To	Literal Number Control Type	Literal Number Relative Cycle	FPGALatencyControlINTEL

Decoration

Extra Operands

Enabling Capabilities

6172

LatencyControlLabelINTEL
Apply to an object of type OpTypePointer or OpTypePipe. If that object is used as the pointer operand by an OpLoad or OpStore instruction (for OpTypePointer) or the pipe operand by an OpReadPipe, OpWritePipe, OpReadPipeBlockingINTEL, or OpWritePipeBlockingINTEL instruction (for OpTypePipe) then this decoration conveys latency control information about that instruction. Any such instructions will be referred to as the "labeled instructions" corresponding to the decoration.

Latency Label is a 32-bit signed integer type scalar that labels the labeled instruction so that it may be referred to in LatencyControlConstraintINTEL decorations.

Literal Number
Latency Label

FPGALatencyControlINTEL

6173

LatencyControlConstraintINTEL
Apply to an object of type OpTypePointer or OpTypePipe. If that object is used as the pointer operand by an OpLoad or OpStore instruction (for OpTypePointer) or the pipe operand by an OpReadPipe, OpWritePipe, OpReadPipeBlockingINTEL, or OpWritePipeBlockingINTEL instruction (for OpTypePipe) then this decoration conveys latency control information about that instruction. Any such instructions will be referred to as the "constrained instructions" corresponding to the decoration.

Relative To, Control Type, and Relative Cycle constrain the cycle on which the constrained instruction can be scheduled.

Relative To is a 32-bit signed integer type scalar that identifies the labeled instruction relative to which the constrained instruction associated with this decoration is being constrained. It corresponds to the Latency Label operand of a LatencyControlLabelINTEL decoration.

Relative Cycle is a 32-bit signed integer type scalar whose meaning depends on Control Type.

Control Type is a 32-bit signed integer type scalar that represents the type of the constraint.

If Control Type is equal to 1, it indicates that the latency between the labeled instruction and the constrained instruction should be exactly Relative Cycle cycles.

If Control Type is equal to 2, it indicates that the latency between the labeled instruction and the constrained instruction should be at most Relative Cycle cycles.

If Control Type is equal to 3, it indicates that the latency between the labeled instruction and the constrained instruction should be at least Relative Cycle cycles.

Literal Number
Relative To

Literal Number
Control Type

Literal Number
Relative Cycle

FPGALatencyControlINTEL

Note that both of these decorations are ignored for target devices that are not FPGA.

Capability

Modify Section 3.31, Capability, adding a row to the Capability table:

Capability	Implicitly Declares
6171	FPGALatencyControlINTEL

Capability

Implicitly Declares

6171

FPGALatencyControlINTEL

Issues

None.

Revision History

Rev	Date	Author	Changes
1	2022-11-28	Shuo Niu	Initial public release

Rev

Date

Author

Changes

2022-11-28

Shuo Niu

Initial public release