Name Strings
SPV_INTEL_tensor_float32_conversion
Contact
To report problems with this extension, please open a new issue at:
Contributors
-
Dmitry Sidorov, Intel
-
Victor Mustya, Intel
-
Kacper Kasper, Intel
-
Ben Ashbaugh, Intel
Notice
Copyright (c) 2025 Intel Corporation. All rights reserved.
Status
-
Complete
Version
Last Modified Date |
2025-03-14 |
Revision |
3 |
Dependencies
This extension is written against the SPIR-V Specification, Version 1.6 Revision 5.
This extension requires SPIR-V 1.0.
Overview
This extension adds rounding instruction from float to tensor float (TF32) data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead instruction below uses 32-bit float type to represent TF32 value.
Extension Name
To use this extension within a SPIR-V module, the appropriate OpExtension must be present in the module:
OpExtension "SPV_INTEL_tensor_float32_conversion"
Modifications to the SPIR-V Specification, Version 1.6
Capabilities
Modify Section 3.31, Capability, adding rows to the Capability table:
Capability | Implicitly Declares | |
---|---|---|
6425 |
TensorFloat32RoundingINTEL |
Instructions
3.56.11. Conversion Instructions
OpRoundFToTF32INTEL |
Capability: |
|||
4 |
6426 |
<id> |
Result <id> |
<id> |
Issues
Revision History
Rev | Date | Author | Changes |
---|---|---|---|
1 |
2022-08-22 |
Dmitry Sidorov |
Initial revision |
2 |
2023-02-09 |
Dmitry Sidorov |
Rename the instruction and the extension |
3 |
2025-03-14 |
Dmitry Sidorov |
Clarify rounding mode |