#include "TTL/TTL_c/TTL_macros.h"
#include "TTL_schemes_common.h"

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Data Structures
struct	TTL_simplex_buffering< TENSORTYPE >

Detailed Description

TTL_simplex_buffering pipelines a pair of import and export transactions using three internal buffers, in rotation: each buffer interchangeably serves as input buffer and output buffer, such that in each iteration one buffer is used both to export then import and two buffers are used by compute for reading and writing.

With simplex buffering we're only waiting for previous iterations, so DMA transactions run mostly in parallel to computation, but serially with each other. Using the same buffer both for import and export is possible allowing us to overlap exporting from and importing to the same buffer.

The following table draws the pipelined actions performed in simplex buffering. It specifies which tile is processed in each iteration:

Action\Iteration	#-1	#0	#1	#2	#i (2:NumOfTiles-2)	#NumOfTiles-1	#NumOfTiles	#NumOfTiles+1
WaitExport				0	i-2	NumOfTiles-3	NumOfTiles-2	NumOfTiles-1
Export			0	1	i-1	NumOfTiles-2	NumOfTiles-1
Wait Import		0	1	2	i	NumOfTiles-1
Import	0	1	2	3	i+1
Compute		0	1	2	i	NumOfTiles-1

Notice the prolog (at iteration number -1) and the 2 epilogs (at iterations number NumOfTiles and NumOfTiles+1) which add in total 3 extra iterations.

Definition in file p/pipelines/TTL_simplex_scheme.h.

Data Structures

Detailed Description